Technology advancements have enabled the integration of large on-die embedded Dynamic Random Access Memory (eDRAM) caches with a Central Processing Unit (CPU). Embedded DRAM is significantly denser than traditional Static Random Access Memories (SRAMs), but must be periodically refreshed to retain data. Like SRAM, embedded DRAM is susceptible to device variations, which play a role in determining a refresh period for embedded DRAM cells. Power consumed to refresh eDRAM represents a large portion of overall system power, particularly during low-power states when the CPU is idle.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments of the claimed subject matter, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly, and be defined only as set forth in the accompanying claims.